AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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6
7
LCD_AC_BIAS_EN
8
LCD_VSYNC
LCD_HSYNC
9
10
10
11
1
3
2
LCD_PCLK
(passive mode)
4
5
LCD_DATA[7:0]
1, L 2, L
P, L
1, 1 2, 1
P, 1
(passive mode)
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
1, L 2, L
P, L
(active mode)
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
16 x (1 to 2048)
Line L
Line 1 (Passive Only)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-84. LCD Raster-Mode Control Signal Activation
206
Peripheral Information and Timings
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