AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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CS_DELAY
(0 to 3)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
4
5
LCD_DATA[15:0]
Write Data
20
10
LCD_VSYNC
(RS)
10
11
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-72. Data Write in Hitachi Mode
R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
17
16
15
8
14
8
LCD_DATA[15:0]
Read Command
18
LCD_VSYNC
(RS)
9
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-73. Command Read in Hitachi Mode
194
Peripheral Information and Timings
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