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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
17
16
15
14
LCD_DATA[15:0]
Read Data
18
LCD_VSYNC
(RS)
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-74. Data Read in Hitachi Mode
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Peripheral Information and Timings
195
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