AM3352BZCZD80 参数 Datasheet PDF下载

型号：	AM3352BZCZD80
PDF下载：	下载PDF文件查看货源
内容描述：	的Sitara AM335x ARM Cortex-A8的微处理器（MPU ） [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用：	微控制器和处理器外围集成电路微处理器时钟
文件页数/大小：	236 页 / 2887 K
品牌：	TI [ TEXAS INSTRUMENTS ]

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F –OCTOBER 2011–REVISED APRIL 2013

Table 5-30. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode

OPP100

MIN

OPP50

MIN

NO.

PARAMETER

UNIT

MAX

t_R(d)

Rise time, output data gpmc_ad[15:0]

Fall time, output data gpmc_ad[15:0]

t_F(d)

GNF0 t_w(wenV)

Pulse duration, output write enable gpmc_wen

valid

Delay time, output chip select gpmc_csn[x]⁽¹³⁾

valid to output write enable gpmc_wen valid

A⁽¹⁾

B⁽²⁾- 5

C⁽³⁾- 5

GNF1 t_d(csnV-wenV)

GNF2 t_w(cleH-wenV)

B⁽²⁾- 0.2

B⁽²⁾+ 2.0

B⁽²⁾+ 5

C⁽³⁾+ 5

Delay time, output lower-byte enable and

command latch enable gpmc_be0n_cle high to

output write enable gpmc_wen valid

C⁽³⁾- 0.2 C⁽³⁾+ 2.0

D⁽⁴⁾- 0.2 D⁽⁴⁾+ 2.0

GNF3 t_w(wenV-dV)

GNF4 t_w(wenIV-dIV)

GNF5 t_{w(wenIV-cleIV)}

Delay time, output data gpmc_ad[15:0] valid to

output write enable gpmc_wen valid

D⁽⁴⁾- 5

E⁽⁵⁾- 5

F⁽⁶⁾- 5

D⁽⁴⁾+ 5

E⁽⁵⁾+ 5

F⁽⁶⁾+ 5

Delay time, output write enable gpmc_wen

invalid to output data gpmc_ad[15:0] invalid

E⁽⁵⁾- 0.2

F⁽⁶⁾- 0.2

E⁽⁵⁾+ 5

Delay time, output write enable gpmc_wen

invalid to output lower-byte enable and command

latch enable gpmc_be0n_cle invalid

F⁽⁶⁾+ 2.0

GNF6 t_{w(wenIV-csnIV)}

GNF7 t_w(aleH-wenV)

GNF8 t_{w(wenIV-aleIV)}

Delay time, output write enable gpmc_wen

invalid to output chip select gpmc_csn[x]⁽¹³⁾

invalid

G⁽⁷⁾- 0.2 G⁽⁷⁾+ 2.0

C⁽³⁾- 0.2 C⁽³⁾+ 2.0

G⁽⁷⁾- 5

C⁽³⁾- 5

F⁽⁶⁾- 5

G⁽⁷⁾+ 5

C⁽³⁾+ 5

F⁽⁶⁾+ 5

Delay time, output address valid and address

latch enable gpmc_advn_ale high to output write

enable gpmc_wen valid

Delay time, output write enable gpmc_wen

invalid to output address valid and address latch

enable gpmc_advn_ale invalid

F⁽⁶⁾- 0.2

F⁽⁶⁾+ 2.0

GNF9 t_c(wen)

Cycle time, write

Delay time, output chip select gpmc_csn[x]⁽¹³⁾

valid to output enable gpmc_oen valid

H⁽⁸⁾

I⁽⁹⁾+ 2.0

H⁽⁸⁾

I⁽⁹⁾+ 5

GNF10 t_d(csnV-oenV)

I⁽⁹⁾- 0.2

I⁽⁹⁾- 5

GNF13 t_w(oenV)

GNF14 t_c(oen)

Pulse duration, output enable gpmc_oen valid

Cycle time, read

K⁽¹⁰⁾

L⁽¹¹⁾

M⁽¹²⁾- 0.2 M⁽¹²⁾+ 2.0

L⁽¹¹⁾

M⁽¹²⁾- 5

GNF15 t_{w(oenIV-csnIV)}

Delay time, output enable gpmc_oen invalid to

output chip select gpmc_csn[x]⁽¹³⁾invalid

M⁽¹²⁾+ 5

(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK⁽¹⁴⁾

(2) B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(3) C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾

(5) E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay) * GPMC_FCLK⁽¹⁴⁾

(6) F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(7) G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾

(9) I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK⁽¹⁴⁾

(12) M = ((CSRdOffTime - OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay)) * GPMC_FCLK⁽¹⁴⁾

(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Peripheral Information and Timings

145

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