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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csn[x]
FA9
Address (MSB)
FA0
gpmc_a[27:17]
FA10
gpmc_be0n_cle
Valid
FA0
FA10
gpmc_be1n
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen
FA29
FA37
Data IN
Data IN
Address (LSB)
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-26. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word
142
Peripheral Information and Timings
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