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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
GPMC_FCLK
gpmc_clk
gpmc_csn[x]
gpmc_a[10:1]
FA5
FA5
FA1
FA1
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen
Data Upper
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-23. GPMC and NOR Flash—Asynchronous Read—32-bit
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Peripheral Information and Timings
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