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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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GPMC_FCLK
gpmc_clk
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
gpmc_csn[x]
gpmc_a[10:1]
FA9
Add0
Add4
FA0
FA10
FA10
gpmc_be0n_cle
FA0
gpmc_be1n
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen
D3
D0
D1
D2
D3
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-24. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-bit
140
Peripheral Information and Timings
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