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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
5.6.1.2 GPMC and NOR Flash—Asynchronous Mode
Table 5-24 and Table 5-25 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-22 through Figure 5-27).
Table 5-23. GPMC and NOR Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-24. GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
FI1 Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI2 Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
4
6.5
6.5
6.5
6.5
4
6.5
6.5
6.5
6.5
ns
ns
ns
ns
ns
FI3 Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
FI4 Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
FI5 Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
FI6 Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle,
output upper-byte enable gpmc_be1n generation from internal functional clock
GPMC_FCLK(3)
FI7 Delay time, output enable gpmc_oen generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
ps
FI8 Delay time, output write enable gpmc_wen generation from internal functional
clock GPMC_FCLK(3)
FI9 Skew, internal functional clock GPMC_FCLK(3)
100
100
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Copyright © 2011–2013, Texas Instruments Incorporated
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