ADS8284
www.ti.com................................................................................................................................................................................................... SLAS628–MARCH 2009
t
w1
t
w2
CONVST
t
t
pd2
pd1
t
w4
t
w3
BUSY
t
t
w7
su1
t
d7
CS
t
pd3
t
d6
†
CONVERT
t
(CONV)
t
(CONV)
t
(HOLD)
†
SAMPLING
(When CS Toggle)
t
(ACQ)
t
t
su(ABORT)
su(ABORT)
BYTE
t
t
h1
su5
BUS 18/16
t
pd4
t
h2
RD = 0
t
en
t
en
t
dis
t
dis
t
en
Repeated
Previous
D[17:12]
MSB
D[17:12]
Hi−Z
Hi−Z
Hi−Z
D[17:12]
D[9:4]
D[3:2]
DB[17:12]
DB[11:10]
Repeated
D[11:10]
Previous
D[11:10]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
D[11:10]
D[1:0]
Repeated
D [9:0]
Previous
D [9:0]
D[9:0]
DB[9:0]
†
Signal internal to device
Figure 3. Timing for Conversion and Acquisition Cycles with CS Toggling, RD Tied to BDGND
Copyright © 2009, Texas Instruments Incorporated
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