ADS8284
SLAS628–MARCH 2009................................................................................................................................................................................................... www.ti.com
It is recommended (not mandatory) to short the BUSY output of the device to the MXCLK input. The device
selects a new channel at every rising edge of MXCLK. The multiplexer is differential. The multiplexer and ADC
driver are designed to settle to the 18-bit level before sampling; even at the maximum conversion speed.
ADC control and timing: The timing diagrams in this section describe ADC operation; multiplexer operation is
described in a later section.
t
w2
t
w1
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
t
w7
t
su1
t
d7
CS
t
t
d6
pd3
†
CONVERT
t
(CONV)
t
(CONV)
t
(HOLD)
†
SAMPLING
(When CS Toggle)
t
(ACQ)
t
t
su(ABORT)
su(ABORT)
BYTE
t
su5
t
h1
BUS 18/16
t
su5
t
t
pd4
su2
t
h2
t
d1
RD
DB[17:12]
DB[11:10]
t
dis
t
en
Hi−Z
Hi−Z
D[17:12] D[9:4]
MSB
Hi−Z
Hi−Z
Hi−Z
Hi−Z
D[11:10] D[3:2]
D[1:0]
D[9:0]
DB[9:0]
†
Signal internal to device
Figure 2. Timing for Conversion and Acquisition Cycles with CS and RD Toggling
12
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