ADS8284
www.ti.com................................................................................................................................................................................................... SLAS628–MARCH 2009
PIN ASSIGNMENTS
QFN PACKAGE
(TOP VIEW)
16 15 14 13 12 11 10
17
9
8
7
6
5
4
3
2
1
64
CH0P
CH0M
CH1P
CH1M
PD-RBUF
VEE
BUS18_16
+VBD
BUSY
DB0
18
19
20
21
22
23
24
25
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DB1
DB2
DB3
VCC
ADS8284
DB4
VCC
DB5
INP
DB6
AGND 26
DB7
INM
NC
27
28
29
DB8
DB9
CH2P
BGND
+VBD
DB10
CH2M 30
CH3P
CH3M
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
PIN FUNCTIONS
PIN
NAME
MULTIPLEXER INPUT PINS
I/O
DESCRIPTION
NO
Non-inverting analog input for differential multiplexer channel number 0. Device performance is optimized for 50-Ω source
impedance at this input.
17
18
19
20
29
30
31
32
CH0P
CH0M
CH1P
CH1M
CH2P
CH2M
CH3P
CH3M
I
I
I
I
I
I
I
I
Inverting analog input for differential multiplexer channel number 0. Device performance is optimized for 50-Ω source
impedance at this input.
Non-inverting analog input for differential multiplexer channel number 1. Device performance is optimized for 50-Ω source
impedance at this input.
Inverting analog input for differential multiplexer channel number 1. Device performance is optimized for 50-Ω source
impedance at this input.
Non-inverting analog input for differential multiplexer channel number 2. Device performance is optimized for 50-Ω source
impedance at this input.
Inverting analog input for differential multiplexer channel number 2. Device performance is optimized for 50-Ω source
impedance at this input.
Non-inverting analog input for differential multiplexer channel number 3. Device performance is optimized for 50 ohm source
impedance at this input.
Inverting analog input for differential multiplexer channel number 3. Device performance is optimized for 50-Ω source
impedance at this input.
ADC INPUT PINS
25
27
INP
INM
I
I
ADC Non inverting input., connect 1-nF capacitor across INP and INM
ADC Inverting input, connect 1-nF capacitor across INP and INM
REFERENCE INPUT/ OUTPUT PINS
8, 9
10
REFM
REFIN
I
I
Reference ground.
Reference Input. Add 0.1-µF decoupling capacitor between REFIN and REFM.
Reference Output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used.
11
REFOUT
O
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