ADS8284
www.ti.com................................................................................................................................................................................................... SLAS628–MARCH 2009
t
w2
t
w1
CONVST
t
t
pd2
pd1
t
w4
t
w3
BUSY
CS = 0
†
CONVERT
t
t
(CONV)
(CONV)
t
pd3
t
pd3
t
(HOLD)
t
(HOLD)
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(ABORT)
su(ABORT)
BYTE
t
t
su5
su5
BUS 18/16
t
t
su5
su5
t
h1
t
h1
RD = 0
t
d5
D[17:12]
D[11:10]
D[9:0]
D[9:4]
D[3:2]
Next D[17:12]
DB[17:12]
DB[11:10]
D[1:0]
Next D[11:10]
Next D[9:0]
Previous LSB
DB[9:0]
†
Signal internal to device
Figure 5. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read
Copyright © 2009, Texas Instruments Incorporated
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