ADS8284
SLAS628–MARCH 2009................................................................................................................................................................................................... www.ti.com
t
w1
t
w2
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
CS = 0
†
CONVERT
t
t
(CONV)
(CONV)
t
(HOLD)
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(ABORT)
su(ABORT)
BYTE
t
su5
t
h1
BUS 18/16
t
su5
t
pd4
t
h2
RD
t
dis
t
en
MSB
Hi−Z
Hi−Z
D[17:12] D[9:4]
DB[17:12]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
D[11:10] D[3:2]
D[1:0]
DB[11:10]
DB[9:0]
D[9:0]
†
Signal internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
14
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