ADS7864
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SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
t11
t10
BUSY
t4
CLOCK
HOLDB
CS
RD
A0
Figure 27. Timing of One Conversion Cycle
READING DATA (RD, CS)—In general, the chan-
nel/data outputs are in tristate. Both CS and RD have
to be low to enable these outputs. RD and CS have
to stay low together for at least 30ns (see Figure 28,
t13) before the output data is valid. RD has to remain
high for at least 30ns (see Figure 28, t14) before
bringing it back low for a subsequent read command.
BUSY
CLOCK
12.5 clock-cycles after the start of a conversion
(BUSY going low), the new data is latched into its
output register. If a read process is initiated around
12.5 clock cycles after BUSY went low, RD and CS
should stay low for at least 50ns to get the new data
stored to its register and switched to the output.
t1
t4
HOLDB
CS being low tells the ADS7864 that the bus on the
board is assigned to the ADS7864. If an A/D con-
verter shares a bus with digital gates, there is a
possibility that digital (high frequency) noise may be
coupled into the A/D converter. If the bus is just used
by the ADS7864, CS can be hardwired to ground.
Reading data at the falling edge of one of the hold
signals might cause distortion of the hold value.
t13
CS
RD
t14
t12
A0
Figure 28. Timing for Reading Data
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