ADS7864
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SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
BIPOLAR INPUTS
Hold signals. The FIFO mode will allow the six
registers to be used by a single channel pair, and
therefore three locations for CH X0 and three lo-
cations for CH X1 can be acquired before they are
read from the part.
The differential inputs of the ADS7864 were designed
to accept bipolar inputs (–VREF and +VREF) around the
internal reference voltage (2.5V), which corresponds
to a 0V to 5V input range with a 2.5V reference. By
using a simple op amp circuit featuring a single
amplifier and four external resistors, the ADS7864
can be configured to accept bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can
be interfaced to the ADS7864 using the resistor
values shown in Figure 25.
EXPLANATION OF CLOCK, RESET AND
BUSY PINS
CLOCK—An external clock has to be provided for the
ADS7864. The maximum clock frequency is 8MHz.
The minimum clock cycle is 125ns (see Figure 26, t5),
and the clock has to remain high (see Figure 26, t6)
or low (see Figure 26, t7) for at least 40ns.
R1
Ω
4k
CLOCK
HOLDA
t6
t1
+IN
OPA340
Ω
20k
t7
t5
Bipolar Input
−
IN
ADS7864
t3
R2
REFOUT (pin 33)
2.5V
BIPOLAR INPUT
R1
R2
HOLDB
HOLDC
t9
±
Ω
Ω
5k
10V
1k
2k
4k
±
Ω
Ω
Ω
Ω
5V
10k
20k
±
2.5V
t2
Figure 25. Level Shift Circuit for Bipolar Input
Ranges
t8
RESET
TIMING AND CONTROL
The ADS7864 uses an external clock (CLOCK, pin
22) which controls the conversion rate of the CDAC.
With an 8MHz external clock, the A/D sampling rate
is 500kHz which corresponds to a 2µs maximum
throughput time.
Figure 26. Start of the Conversion
RESET—Bringing reset low will reset the ADS7864. It
will clear all the output registers, stop any actual
conversions and will close the sampling switches.
Reset has to stay low for at least 20ns (see Fig-
ure 26, t8). The reset should be back high for at least
20ns (see Figure 26, t9), before starting the next
conversion (negative hold edge).
THEORY OF OPERATION
The ADS7864 contains two 12-bit A/D converters that
operate simultaneously. The three hold signals
(HOLDA, HOLDB, HOLDC) select the input MUX and
initiate the conversion. A simultaneous hold on all six
channels can occur with all three hold signals strobed
together. The converted values are saved in six
registers. For each read operation the ADS7864
outputs 16 bits of information (12 Data, 3 Channel
Address and Data Valid). The Address/Mode signals
(A0, A1, A2) select how the data is read from the
ADS7864. These Address/Mode signals can define a
selection of a single channel, a cycle mode that
cycles through all channels or a FIFO mode that
sequences the data determined by the order of the
BUSY—Busy goes low when the internal A/D con-
verters start a new conversion. It stays low as long as
the conversion is in progress (see Figure 27, 13
clock-cycles, t10) and rises again after the data is
latched to the output register. With Busy going high,
the new data can be read. It takes at least 16 clock
cycles (see Figure 27, t11) to complete conversion.
START OF A CONVERSION
By bringing one or all of the HOLDX signals low, the
input data of the corresponding channel X is immedi-
ately placed in the hold mode (5ns). The conversion
of this channel X follows as soon as the A/D
converter is available for the particular channel. If
14
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