ADS7864
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SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
other channels are already in the hold mode but not
converted, then the conversion of channel X is put in
the queue until the previous conversion has been
completed. If more than one channel goes into hold
mode within one clock cycle, then channel A will be
converted first if HOLDA is one of the triggered hold
signals. Next, channel B will be converted, and last,
channel C. If it is important to detect a hold command
during a certain clock cycle, then the falling edge of
the hold signal has to occur at least 10ns before the
falling edge of the clock. (see Figure 26, t1). The hold
signal can remain low without initiating a new conver-
sion. The hold signal has to be high for at least 15ns
(see Figure 26, t2) before it is brought low again and
hold has to stay low for at least 20ns (see Figure 26,
t3).
Once a particular hold signal goes low, further im-
pulses of this hold signal are ignored until the
conversion is finished or the part is reset. When the
conversion is finished (BUSY signal goes high), the
sampling switches will close and sample the selected
channel. The start of the next conversion must be
delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the
driving amplifier, but should be at least 175ns
(see Figure 27, t4).
The ADS7864 can also convert one channel continu-
ously, as it is shown in Figure 27 with channel B.
Therefore, HOLDA and HOLDC are kept high all the
time. To gain acquisition time, the falling edge of
HOLDB takes place just before the falling edge of
clock. One conversion requires 16 clock cycles. Here,
data is read after the next conversion is initiated by
HOLDB. To read data from channel B, A1 is set high
and A2 is low. As A0 is low during the first reading
(A2 A1 A0 = 010) data B0 is put to the output. Before
the second RD, A0 switches high (A2 A1 A0 = 011)
so data from channel B1 is read.
In the example of Figure 26, the signal HOLDB goes
low first and channel B0 and B1 will be converted
first. The falling edges of HOLDA and HOLDC occur
within the same clock cycle. Therefore, the channels
A0 and A1 will be converted as soon as the channels
B0 and B1 are finished (plus acquisition time). When
the A-channels are finished, the C-channels will be
converted. The second HOLDA signal is ignored, as
the A-channels are not converted at this point in time.
Table 1. Timing Specifications
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
t1
t2
HOLD (A, B, C) before falling edge of clock
HOLD high time to be recognized again
HOLD low time
10
15
ns
t3
20
ns
t4
Input capacitor charge time
Clock period
175
125
40
ns
t5
ns
t6
Clock high time
ns
t7
Clock low time
40
ns
t8
Reset pulse width
20
ns
t9
First hold after reset
20
ns
t10
t11
t12
t13
t14
Conversion time
12.5 × t5
ns
Successive conversion time (16 × t5)
Address setup before RD
CS before end of RD
RD high time
2
µs
10
30
30
ns
ns
ns
15
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