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ADS7864YB/2KG4 参数 Datasheet PDF下载

ADS7864YB/2KG4图片预览
型号: ADS7864YB/2KG4
PDF下载: 下载PDF文件 查看货源
内容描述: [6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48, GREEN, PLASTIC, TQFP-48]
分类和应用: 转换器
文件页数/大小: 27 页 / 990 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS7864  
www.ti.com  
SBAS141ASEPTEMBER 2000REVISED MARCH 2005  
GETTING DATA  
from channel A0 is read on the first RD signal, then  
A1 on the second, followed by B0, B1, C0 and finally  
C1 before reading A0 again. Data from channel A0 is  
brought to the output first after a reset-signal or after  
powering the part up.  
The ADS7864 has three different output modes that  
are selected with A2, A1 and A0. A2A1A0 are only  
active when RD and CS are both low. After a reset  
occurs, A2A1A0 are set to 000.  
The third mode is a FIFO mode that is addressed  
with (A2 A1 A0 = 111). Data of the channel that is  
converted first will be read first. So, if a particular  
channel is most interesting and is converted more  
frequently (e.g., to get a history of a particular  
channel) then there are three output registers per  
channel available to store data. When the ADS7864  
is operated in the FIFO mode, an initial RD/CS is  
necessary (after power up and after reset), so that  
the internal address is set to ‘111’, before the first  
conversion starts.  
With (A2 A1 A0) = 000 to 101 a particular channel  
can directly be addressed (see Table 3 and Fig-  
ure 27). The channel address should be set at least  
10ns (see Figure 28, t12) before the falling edge of  
RD and should not change as long as RD is low.  
Table 3. Address/Mode Truth Table  
CHANNEL  
SELECTED/  
MODE  
A2  
0
A1  
0
A0  
0
A0  
If a read process is just going on (RD signal low) and  
new data has to be stored, then the ADS7864 will  
wait until the read process is finished (RD signal  
going high) before the new data gets latched into its  
output register.  
A1  
0
0
1
B0  
B1  
0
1
0
0
1
1
C0  
1
0
0
C1  
1
0
1
At time tA (see Figure 31) the ADS7864 resets. With  
the reset signal, all conversions and scheduled con-  
versions are cancelled. The data in the output regis-  
ters are also cleared. With a reset, a running conver-  
sion gets interrupted and all channels go into the  
sample mode again.  
Cycle Mode  
FIFO Mode  
1
1
0
1
1
1
With (A2 A1 A0) = 110 the interface is running in a  
cycle mode (see Figure 29 and Figure 30). Here, data  
RESET  
CLOCK  
HOLDA  
HOLDB  
HOLDC  
tA  
tB  
tC  
tD tE tF  
Figure 31. Example of Hold Signals  
18