ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com
N + 24
N + 4
N + 3
N + 23
N + 2
Sample
N
N + 1
N + 22
Input
Signal
ta
CLKM
CLKP
Input
Clock
tPDI
CLKOUTM
CLKOUTP
22 Clock Cycles
DDR
LVDS
Output Data
DXP, DXM
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E – Even Bits D0,D2,D4,...
O – Odd Bits D1,D3,D5,...
N – 22
N – 21
N – 20
N – 19
N – 1
N
N + 1
tPDI
CLKOUT
Parallel
CMOS
22 Clock Cycles
Output Data
D0–D13
N – 22
N – 21
N – 20
N – 19
N – 18
N – 1
N
N + 1
N + 2
T0105-11
Figure 4. Latency Diagram
CLKP
Input
Clock
CLKM
tPDI
CLKOUTM
CLKOUTP
Output
Clock
th
tsu
tsu
th
Dn(1)
Dn+1(2)
Output
Data Pair
DAnP/M
DBnP/M
T0106-08
(1) Dn - Bits D0, D2, D4, ...
(2) Dn + 1 - Bits d1, D3, D5, ...
Figure 5. LVDS Interface Timing
12
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