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SBAS502A –DECEMBER 2011–REVISED MARCH 2012
LOFF: Lead-Off Control Register
Address = 03h
BIT 7
BIT 6
BIT 5
BIT 4
1
BIT 3
BIT 2
BIT 1
0
BIT 0
COMP_TH2
COMP_TH1
COMP_TH0
ILEAD_OFF1
ILEAD_OFF0
FLEAD_OFF
This register configures the lead-off detection operation.
Bits[7:5]
COMP_TH[2:0]: Lead-off comparator threshold
These bits determine the lead-off comparator threshold. See the Lead-Off Detection subsection of the ECG-Specific
Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4
Must be set to '1'
Bits[3:2]
ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 6 nA (default)
01 = 22 nA
10 = 6 µA
11 = 22 µA
Bit 1
Bit 0
Must be set to '0'
FLEAD_OFF: Lead-off frequency
This bit selects ac or dc lead-off.
0 = At dc lead-off detect (default)
1 = At ac lead-off detect at fDR/4 (500 Hz for an 2-kHz output rate)
Copyright © 2011–2012, Texas Instruments Incorporated
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