ADS1291
ADS1292
ADS1292R
SBAS502A –DECEMBER 2011–REVISED MARCH 2012
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START
The START pin must be set high or the START command sent to begin conversions. When START is low or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and
ADS1292R feature two modes to control conversion: continuous mode and single-shot mode. The mode is
selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is
used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for
more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that
data are ready. Figure 37 shows the timing diagram and Table 11 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Refer to Table 10 for the settling time as a function of tMOD. Note that when START is held high and
there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are
available on the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is
recommended to add one tMOD cycle delay before issuing SCLK to retrieve data.
tSETTLE
START Pin
or
START Opcode
DIN
tDR
4/fCLK
DRDY
(1) Settling time uncertainty is one tMOD cycle.
Figure 37. Settling Time
Table 11. Settling Time for Different Data Rates
DR[2:0]
000
SETTLING TIME(1)
UNIT(2)
tMOD
tMOD
tMOD
tMOD
tMOD
tMOD
tMOD
—
4100
2052
1028
516
260
132
68
001
010
011
100
101
110
111
—
(1) Settling time uncertainty is one tMOD cycle.
(2) tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1.
30
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