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ADS1299 参数 Datasheet PDF下载

ADS1299图片预览
型号: ADS1299
PDF下载: 下载PDF文件 查看货源
内容描述: 低噪声, 8通道, 24位模拟前端的生物电位测量 [Low-Noise, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements]
分类和应用:
文件页数/大小: 66 页 / 1683 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS1299  
SBAS499A JULY 2012REVISED AUGUST 2012  
www.ti.com  
RREG: Read From Register  
This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data  
output. The first byte contains the command opcode and register address. The second opcode byte specifies the  
number of registers to read – 1.  
First opcode byte: 001r rrrr, where r rrrr is the starting register address.  
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.  
The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 44. When  
the device is in read data continuous mode, an SDATAC command must be issued before the RREG command  
can be issued. The RREG command can be issued any time. However, because this command is a multi-byte  
command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock  
(SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire  
command.  
CS  
1
9
17  
25  
SCLK  
DIN  
OPCODE 1  
OPCODE 2  
REG DATA  
REG DATA + 1  
DOUT  
Figure 44. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)  
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)  
WREG: Write to Register  
This opcode writes register data. The Register Write command is a two-byte opcode followed by the register data  
input. The first byte contains the command opcode and register address. The second opcode byte specifies the  
number of registers to write – 1.  
First opcode byte: 010r rrrr, where r rrrr is the starting register address.  
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.  
After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 45. The WREG  
command can be issued any time. However, because this command is a multi-byte command, there are SCLK  
rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI  
Interface section for more details. Note that CS must be low for the entire command.  
CS  
1
9
17  
25  
SCLK  
DIN  
OPCODE 1  
OPCODE 2  
REG DATA 1  
REG DATA 2  
DOUT  
Figure 45. WREG Command Example: Write Two Registers Starting from 00h (ID Register)  
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)  
38  
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): ADS1299  
 
 
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