78Q8430 Data Sheet
DS_8430_001
10 System Bus Interface Schematic
+3.3V
VCC
ADDR9
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RESET
BUSCLK
CS
WR
OE
78Q8430
Single Chip
10/100 Ethernet
MAC & PHY
MEMWAIT
INT
PME
DATA8
DATA7
ENDIAN1
ENDIAN0
DATA6
DATA5
DATA4
BOOTSZ1
BOOTSZ0
BUSMODE
CLKMODE
WAITMODE
DATA3
DATA2
DATA1
DATA0
PROMCLK
PROMCS
PROMDO
PROMDI
Optional
External
EEPROM
TCLK
TRST
TMS
TDO
TDI
Optional
JTAG
BSDL
Interface
GND
BOOTSZ[1:0]
00 - bus is 32-bit wide
01 - bus is 16-bit wide
10 - bus is 8-bit wide
ENDIAN[1:0]
0,0 = Big Endian (MSB at high bit positions)
1,1 = Little Endian (MSB at low bit positions)
BUSMODE, CLKMODE, WAITMODE
0,0,0 = sync bus, ext. system clock, memwait act low
0,0,1 = sync bus, ext. system clock, memwait act high
1,0,0 = async bus, ext. system clock, memwait act low
1,0,1 = async bus, ext. system clock, memwait act high
1,1,0 = async bus, int. system clock, memwait act low
1,1,1 = async bus, int. system clock, memwait act high
Figure 15: System Bus Interface Schematic
84
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
