DS_8430_001
78Q8430 Data Sheet
6.12 PHY Operations
6.12.1 Automatic MDI/MDIX Cable Crossover Configuration
The transmitter and receiver contain logic and mux to detect and correct for cross over cabling errors.
The implementation is fully compliant with IEEE 802.3 specifications, ensuring interoperation with other
PHYs, which may or may not implement automatic MDI/MDI-X configuration. The automatic MDI/MDI-X
state machine facilitates switching TXN and TXP pins with the RXN and RXP pins, prior to the auto-
negotiation mode of operation. The correct polarization of the crossover circuit is determined by an
algorithm that controls the switching function. Use of an 11-bit Linear Feedback Shift Register (LFSR)
creates a pseudo-random sequence to determine the MDI configuration. Upon making the selection to
either MDI or MDI-X, the 78Q8430 waits for a specified amount of time while evaluating its receive
channel to determine whether the other end of the link is sending link pulses or 10BASE-T or
100BASE-TX data. If link pulses or data are detected, the 78Q8430 remains in that configuration. If link
pulses or data are not detected, it increments it’s LFSR and makes a decision to switch based on the
value of the next bit. The state machine does not move from one state to another while link pulses are
being transmitted.
6.12.2 100Base-TX Transmit
The 78Q8430 PHY contains all of the necessary circuitry to convert the transmit MII signaling from a MAC
to an IEEE-802.3 compliant data-stream driving Cat-5 UTP cabling. The internal PCS interface maps
4-bit nibbles from the MII to 5-bit code groups as defined in Table 24-1 of IEEE-802.3. The 5-bit code
groups are then scrambled and converted to a serial stream before being sent to the MLT-3 pulse
shaping circuitry and line driver. The pulse-shaper uses current modulation to produce the desired output
waveform. Controlled rise/fall time in the MLT-3 signal is achieved using an accurately controlled voltage
ramp generator. The line driver requires an external 1:1 isolation transformer to interface with the line
media. The center-tap of the primary side of the transformer connects to the 3.3 V supply.
6.12.3 100Base-TX Receive
The 78Q8430 PHY receives a 125 MBaud MLT-3 signal through a 1:1 transformer. The signal then goes
through a combination of adaptive offset adjustment (baseline wander correction) and adaptive
equalization. The effect of these circuits is to sense the amount of dispersion and attenuation caused by
the cable and transformer and restore the received pulses to logic levels. The amount of gain and
equalization applied to the pulses varies with the detected attenuation and dispersion and, therefore, with
the length of the cable. The 78Q8430 PHY can compensate for cable loss of up to 10dB at 16 MHz. This
loss is represented as test_chan_5 in Annex A of the ANSI X3.263:1995 specification and corresponds to
approximately 140 m of CAT-5 UTP cabling. The equalized MLT-3 data signal is bi-directionally sliced
and the resulting bit-stream is presented to the CDR where it is re-timed and decoded to NRZ format.
The retimed serial data is converted to parallel, then de-scrambled and aligned into 5 bit code groups.
The receive PCS interface maps these code groups to 4 bit data for the internal MII as outlined in Clause
24 of IEEE-802.3.
6.12.4 10Base-T Transmit
The 78Q8430 PHY takes 4-bit parallel NRZ data via the MII interface and passes it through a parallel to
serial converter. The data is then passed through a Manchester encoder, pre-emphasis pulse-shaper,
media filter and finally to the twisted-pair line driver. The pulse shaper and filter ensures the output
waveforms meet the output voltage template and spectral content requirements detailed in Clause 14 of
IEEE-802.3. Interface to the twisted pair media is through a center-tapped 1:1 transformer. No external
filtering is required. During auto-negotiation and 10BASE-T idle periods, link pulses are transmitted.
The 78Q8430 PHY employs an on board timer to prevent the MAC from capturing a network through
excessively long transmissions. When this timer is exceeded the chip enters the jabber state and
transmission is disabled. The jabber state is exited after the MII goes idle for 500 ms ± 250 ms.
Rev. 1.2
49
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
