78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
REGISTER DESCRIPTION
(continued)
LEGEND
TYPE
R/O
R/C
DESCRIPTION
Read only
Read and Clear
TYPE
R/W
DESCRIPTION
Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
Line Rate Selection:
Selects the line rate of all channels as well as the input clock frequency
at the CKREFP/N pins.
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
Unused
Serial/Parallel Interface Selection:
Selects the interface to the framer.
0: Serial LVPECL
1: 4-bit Parallel CMOS
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential)
10: 77.76MHz / NA (single-ended)
00: 19.44MHz / 17.408MHz (single-ended)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset or power up.
Reserved.
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
7
E4
R/W
0
6
--
R/W
0
5
PAR
R/W
0
4:3
CKSL
[1:0]
R/W
XX
2:1
0
--
SRST
R/W
R/W
X0
0
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
