78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
FUNCTIONAL DESCRIPTION
(continued)
POWER-DOWN FUNCTION
Power-down control is provided to allow the
78P2351 to be shut off. Transmit and receive
power-down can be set independently through SW
control.
Global power-down is achieved by
powering down both the transmitter and receiver.
Note:
the serial interface and configuration
registers are not affected by power-down.
The transmitter can also be powered down using the
TXPD control pin. The CMI outputs are tri-stated
during transmit power-down for redundancy
applications.
The TXPD pin is active in both
hardware and software modes.
LOOPBACK MODES
In SW mode, LLBK and RLBK bits are provided to
activate the local and remote loopback modes
respectively. In HW mode, the LPBK pin can be
used to activate local and remote loopback modes
as shown below.
LPBK pin
Low
Float
Loopback Mode
Normal operation
Remote (digital) Loopback:
Recovered receive clock and data
looped back to transmitter
Local (analog) Loopback:
Transmit clock and data looped back to
receiver
Lock Detect
ECLP/N
SIDP/N
SICKP/N
PICK
PI[3:0]D
PTOCK
Tx CDR
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50us after Vcc reaches 2.4V at power up, a
reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function pin
that allows for the following:
•
•
•
Override the internal POR signal by driving in
an external active low reset signal;
Use the POR signal to drive other IC’s power-
on reset;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2351. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
trimming. The SPSL pin must be high in order to
use the serial port.
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations. It can also be used to select a particular
device allowing SCK_MON, SDI_PAR and SDO_E4
to be bussed together. SCK_MON is the clock input
that times the data on SDI_PAR and SDO_E4. Data
on SDI_PAR is latched in on the rising-edge of
SCK_MON, and data on SDO_E4 is clocked out
using the falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB) first.
The mode and address bit assignment and register
table are shown in the following section.
SDO_E4 is a tristate capable output. It is used to
output register data during a read operation.
SDO_E4 output is normally high impedance, and is
enabled only during the duration when register data
is being clocked out. Read data is clocked out least
significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tristate capable, SDI_PAR and SDO_E4 can be
connected together to simplify connections.
PROGRAMMABLE INTERRUPTS
In addition to the receiver LOS and LOL status pins,
the 78P2351 provides a programmable interrupt for
each transmitter. In HW control mode, the default
functions of the Tx interrupt is a transmit Loss of
Lock (TXLOL) or FIFO error (FERR).
High
FIFO
CMI
Encoder
TXCKP/N
CMI2P/N
CMIP/N
PMOD, SMOD[1:0], PAR
RLBK,
RDSL
SOCKP/N
SODP/N
PO[3:0]D
POCK
CMI
Decoder
Rx CDR
Lock Detect
CMI
Adaptive
Eq.
RXP/N
LOS Detect
LLBK
Figure 7: Local (Analog) Loopback
Lock Detect
ECLP/N
SIDP/N
SICKP/N
PICK
PI[3:0]D
PTOCK
Tx CDR
FIFO
CMI
Encoder
TXCKP/N
CMI2P/N
CMIP/N
PMOD, SMOD[1:0], PAR
RLBK,
RDSL
SOCKP/N
SODP/N
PO[3:0]D
POCK
CMI
Decoder
Rx CDR
Lock Detect
CMI
Adaptive
Eq.
RXP/N
LOS Detect
LLBK
Figure 8: Remote (Digital) Loopback
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
