78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as
required.
DFLT
BIT
7
NAME
INPOL
--
TYPE
R/W
DESCRIPTION
VALUE
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low (default)
1 : Interrupt output is active-high
0
6:2
R/W
01000 Reserved
TXLOL Error Mask (active low):
Gates the TXLOL register bit to the INTTXB interrupt pin.
1
0
MTLOL
MFERR
R/W
R/W
1
1
0: Mask
1: Pass
FIERR Error Mask (active low):
Gates the respective FIERR register bit to the INTTXB interrupt pin.
0: Mask
1: Pass
ADDRESS 0-2: I/O CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
XXXXXXX Unused
7:1
--
R/W
Redundant Channel Enable:
Enables transmit monitor outputs at CMI2P/N pins.
0
RCSL
R/W
0
0: Disable
1: Enable
10
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