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78P2351-IGT/A04/F 参数 Datasheet PDF下载

78P2351-IGT/A04/F图片预览
型号: 78P2351-IGT/A04/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom IC,]
分类和应用:
文件页数/大小: 40 页 / 429 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit  
REGISTER DESCRIPTION (continued)  
PORT-SPECIFIC REGISTERS  
For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and  
the read/write operation will be ignored.  
ADDRESS 1-0: MODE CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Transmitter Power-Down:  
0 : Normal Operation  
7
PDTX  
R/W  
0
1 : Power-Down. CMI Transmit outputs are also tri-stated.  
Receiver Power-Down:  
6
PDRX  
R/W  
0
0 : Normal Operation  
1 : Power-Down  
Parallel Mode Interface Selection:  
When PAR=1, (Master Control Regsiter: bit 5), PMODE selects the  
source of the transmit parallel clock, either taken from the framer  
externally or generated internally. Default value is determined by  
CKMODE pin setting upon power up or reset.  
5
PMODE  
R/W  
X
0: Slave Timing. PICK clock input to the transmitter  
1: Master Timing. PTOCK clock output from the transmitter  
When PAR=0, PMODE is invalid and defaults to logic ‘1’  
Serial Mode Interface Selection:  
When PAR=0 (Master Control Regsiter: bit 5), SMOD[1:0] configures  
the transmitter’s system interface. Default values determined by  
CKMODE pin setting upon power up or reset.  
SMOD[1] SMOD[0]  
4
SMOD[1]  
R/W  
X
0
1
0
0
0
1
Synchronous clock and data are passed through a  
FIFO. The CDR is bypassed.  
Synchronous data is passed through the CDR and  
then through the FIFO.  
Plesiochronous data is passed through the CDR to  
recover a clock. FIFO is bypassed because the  
data is not synchronous with the reference clock.  
Loop Timing Mode Enable: The recovered receive  
clock is used as the reference for the transmitter.  
The transmit data is passed through the CDR, but  
the FIFO is bypassed.  
1
1
3
SMOD[0]  
R/W  
X
When PAR=1, setting SMOD[1:0] = 11 will enabled Loop Timing Mode.  
Default values are determined by CKMODE pin setting upon power up  
or reset as follows:  
CKMODE Low SMOD[1:0] default = 00 (no effect)  
CKMODE Float SMOD[1:0] default = 11 (loop-timing)  
CKMODE High SMOD[1:0] default = 01 (no effect)  
Receive Monitor Mode Enable:  
0: Normal Operation  
1: Adds 20dB of flat gain to the receive signal before equalization.  
NOTE: Monitor mode is only available in CMI mode.  
2
MON  
--  
R/W  
R/W  
0
1:0  
00  
Reserved  
11