78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
REGISTER DESCRIPTION (continued)
ADDRESS 1-1: SIGNAL CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIP/N.
7
TCMIINV
R/W
0
0: Normal
1: Invert
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXP/N.
6
5
RCMIINV
LOLOR
R/W
R/W
0
0
0: Normal
1: Invert
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
0: Normal
1: Forces LOS and LOL outputs to be low and resets LOS counter
Loopback Selection:
RLBK LLBK
4
3
2
RLBK
LLBK
R/W
R/W
R/W
0
0
0
0
1
0
0
Normal operation
Remote Loopback Enable: Recovered receive data
is looped back to the transmitter for retransmission.
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
0
1
Receive Clock Inversion Select:
This bit will invert the receive output clock.
RCLKP
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
Transmit Clock Inversion Select:
This bit will invert the transmit input system clock.
1
0
TCLKP
FRST
R/W
R/W
0
0
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
NOTE: Transmit monitor port will also be affected by FRST
12
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
