FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
V3P3
VARPULSE
WPULSE
DIO2
Internal
3
2
1
OPT_TX
from
OPT_TX UART
A
MOD
B
0
OPT_TXINV
EN DUTY
2
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
B
A
B
1/38kHz
Figure 9: Optical Interface
1.5.7 Digital I/O – 71M6531D/F
The 71M6531D/F includes up to 22 pins of general-purpose digital I/O. These pins are compatible with 5 V
inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DIO pins (1 pin): PB
• DIO/LCD segment pins (a total of 19 pins):
o
o
o
o
DIO4/SEG24 - DIO15/SEG35 (12 pins)
DIO17/SEG37 (1 pin)
DIO28/SEG48 – DIO29/SEG49 (2 pins)
DIO43/SEG63 - DIO46/SEG66 (4 pins)
• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX
The pins DIO4/SEG24 through DIO46/SEG66 are configured by the LCD_BITMAP registers to be DIO or
segment pins. A one in LCD_BITMAP defines the pin as a LCD segment output, a zero makes the pin a
DIO pin. Pins configured as LCD pins are controlled with the LCD_SEGnn registers. Pins configured as
DIO can be defined independently as an input or output with the DIO_DIR bits (see Table 45).
Write operations to a disabled DIO are not ignored. Write operations are registered, but do not affect
the pin, or the result of a read operation on the pin, until it becomes a DIO output.
DIO2/OPT_TX will be an active TX output pin at power up (OPT_TXE[1:0] = 00).
A 3-bit configuration word, I/O RAM field DIO_Rx[2:0] (0x2009[2:0] through 0x200E[6:4]), can be used for
certain pins (when configured as DIO) to individually assign an internal resource such as an interrupt or a
timer control (see Table 46 for DIO pins available for this option). This way, DIO pins can be tracked
even if they are configured as outputs.
Table 39 to Table 41 lists the direction registers and configurability associated with each group of DIO pins.
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