FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Table 39: Data/Direction Registers and Internal Resources for DIO Pin Groups
DIO
PB
–
1
–
2
–
3
3
3
4
5
6
7
8
9
10 11 12* 13 14 15
24 25 26 27 28 29 30 31 32* 33 34 35
44 29 30
22 70 71 72 73 77 78 79 80 120 50 35 36
0*
LCD_BITMAP[39:32]
LCD Segment
71M6533 Pin #
71M6534 Pin #
–
97 91
17 60 61 62 63 67 68 69 70
–
114 109
0
1
2
3
4
5
6
7
1
2
3
Configuration (DIO
or LCD segment)
Always DIO
LCD_BITMAP[31:24]
0
–
1
1
2
3
4
5
6
7
0
1
2
3
4*
DIO1 = P1 (SFR 0x90)
4*
DIO_DIR1 (SFR 0x91)
5
6
6
–
7
7
–
Data Register
DIO0 = P0 (SFR 0x80)
2
3
4
5
6
7
0
1
2
3
5
Direction Register
0 = input, 1 = output
DIO_DIR0 (SFR 0xA2)
–
–
Internal Resources
Configurable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
DIO
16 17 18 19 20 21 22* 23 24 25 26 27 28* 29 30
36 37 38 39 40 41 42* 43 44 45 46 47 48* 49 50
–
–
–
LCD Segment
71M6533 Pin #
71M6534 Pin #
33 12 13 64 65 66
–
54 46 43 42 41
–
32 35
39 17 18 74 75 76 115 64 52 49 48 47 81 38 41
4
5
6
7
0
4
1
5
2*
3
4
5
6
2
7
3
0*
1
2
–
Configuration (DIO
or LCD segment)
LCD_BITMAP[39:32]
LCD_BITMAP[47:40]
LCD_BITMAP[55:48]
4*
0
0
1
1
2
3
6*
6*
7
7
0
1
5
6
–
Data Register
DIO2 = P2 (SFR 0xA0)
DIO3 = P3 (SFR 0xB0)
2
3
4
5
Direction Register
0 = input, 1 = output
DIO_DIR2 (SFR 0xA1)
DIO
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
36* 37* 38* 39*
56* 57* 58* 59*
–
–
–
–
–
41 42* 43 44 45 46* 47
61 62* 63 64 65 66* 67
LCD Segment
71M6533 Pin #
71M6534 Pin #
–
–
–
–
99
117 118 46 37 44
6*
–
40 31 38
–
5
22
27
3
87 88 89 90
0* 1* 2* 3*
5
7
0
1
2*
Configuration (DIO
or LCD segment)
LCD_BITMAP[55:48]
LCD_BITMAP[63:56]
LCD_BITMAP[71:64]
Data Register
–
–
–
–
–
–
–
–
–
Direction Register
0 = input, 1 = output
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
43
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