71M6533/71M6534 Data Sheet
FDS_6533_6534_004
For each multi-use pin, the corresponding LCD_BITMAP[] register (as described in Section 1.4.7 Digital I/O)
is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[] registers is speci-
fied in Section 4.1 I/O RAM Map –Functional Order.
LCD segment data is written to the LCD_SEGn[3:0] I/O RAM registers as described in section 4.2 I/O RAM
Description – Alphabetical Order. Note that even though the register names call out bit numbers 3 to 0
some registers use physical bits 4 to 7.
The LCD drivers are grouped into four commons (COM0 – COM3) and up to 56 (71M6533) or 74
(71M6534) segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14- segments
digits or enunciator symbols.
The segment driver SEG18 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is con-
trolled by LCD_Y. There can be up to four pixels/segments connected to this driver pin. The I/O RAM
register LCD_BLKMAP18[3:0] identifies which pixels, if any, are to blink.
The LCD bias may be compensated for temperature using the LCD_DAC bits in I/O RAM. The bias may
be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and brownout modes, VBAT
in LCD mode). When the LCD_DAC bits are set to 000, the DAC is bypassed and powered down. This
can be used to reduce current in LCD mode.
1.4.9 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversion is available at XRAM address 0x07. BME is ignored and assumed zero when system
power is not available.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
Battery measurement is not very linear but is very reproducible. The best way to perform the calibration
is to set the battery input to the desired failure voltage and then have the MPU firmware record that mea-
surement. After this, the MPU firmware’s battery measurement logic may use the recorded value as the
battery failure limit. The same value can also be a calibration offset for any battery voltage display.
See Section 5.4.5 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
1.4.10 EEPROM Interface
The 71M6533 and 71M6534 provides hardware support for either a two-pin or a three-wire (µ-wire) type
of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.
Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is mul-
tiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX = 1. The MPU
communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to
write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to
EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also as-
serted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged
the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-
pin interface is selected are shown in Table 41.
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