FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Table 38: Bank Switching with FL_BANK[2:0]
71M6534H
71M6533/H
71M6534
Address Range for Lower Bank Address Range for Upper Bank
(0x000-0x7FFF)
(0x8000-0xFFFF)
FL_BANK[1:0] FL_BANK[2:0]
00
01
10
11
000
001
010
011
100
101
110
111
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x8000-0xFFFF
0x10000-0x17FFF
0x18000-0x1FFFF
0x20000-0x27FFF
0x28000-0x2FFFF
0x30000-0x37FFF
0x38000-0x3FFFF
Not applicable
in 71M6533/H
and 71M6534
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE op-
erations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before
the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a
global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion
of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE, is reset whenever the chip is reset. Hardware associated with the bit
permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature
but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program
code is possible
Specifically, when SECURE is set, the following applies:
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
•
Writes to page zero, whether by MPU or ICE are inhibited.
MPU/CE RAM
The 71M6533 and 71M6534 includes 4K-bytes of static RAM memory on-chip (XRAM) plus 256 bytes of
internal RAM in the MPU core. The 4K-bytes of static RAM are used for data storage for both MPU and
CE operations.
1.4.6 UART and Optical Interface
In addition to the regular UART (UART0) the device includes an interface to implement an IR/optical port.
The pin OPT_TX is designed to directly drive an external LED for transmitting data on an optical link. The
pin OPT_RX has the same threshold as the RX pin, but can also be used to sense the input from an ex-
ternal photo detector used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a
dedicated UART port (UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, re-
spectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available when
system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. The duty
cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25%
duty cycle means OPT_TX is low for 6.25% of the period. Figure 8 illustrates the OPT_TX generator.
v1.1
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