FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Table 40: Selectable Resources using the DIO_Rn Bits
DIO_Rn
Resource Selected for DIO Pin
None
0
1
2
3
4
5
6
7
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown
in Figure 9, right), not source it from V3P3D (as shown in Figure 9, left). This is due to the re-
sistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
71M6533/71M6534
71M6533
71M6533/71M6534
V3P3SYS
V3P3SYS
VBAT
3.3V
3.3V
VBAT
LED
V3P3D
V3P3D
DIO1
DIO1
R
R
LED
DGND
DGND
Recommended
Not recommended
Figure 9: Connecting an External Load to DIO Pins
1.4.8 LCD Drivers
The device contains a total of 57 (71M6533) or 75 (71M6534) dedicated and multiplexed LCD drivers,
which are grouped as follows:
•
•
•
•
15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 to SEG18, SEG20 to SEG23)
4 drivers multiplexed with the SPI port (SEG3 to SEG6)
2 drivers multiplexed with MUX_SYNC and CKTEST (SEG7 and SEG19)
3 or 8 drivers multiplexed with the ICE interface
o
o
71M6533 – 3 drivers (SEG9 to SEG11)
71M6534 – 8 drivers (SEG9 to SEG11 and SEG51 to SEG55)
•
33 or 46 multi-use LCD/DIO pins described in Section 1.4.7 Digital I/O
o
o
71M6533 – 33 pins
71M6534 – 46 pins
With a minimum of 15 driver pins always available and a total of 57 (71M6533) or 75 (71M6534) driver
pins in the maximum configuration, the device is capable of driving between 60 to 228 pixels (71M6533)
or 60 to 300 pixels (71M6534) of an LCD display with 25% duty cycle. At eight pixels per digit, this cor-
responds to 7.5 to 28 digits for the 71M6533 or 7.5 to 37 digits for the 71M6534.
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