FDS_6533_6534_004
71M6533/71M6534 Data Sheet
terrupt, and must finish before the next one second boundary. The rate adjustment will be implemented
starting at the next one-second boundary. Since the LSB results in an adjustment every four seconds,
the frequency should be measured over an interval that is a multiple of four seconds.
To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency
by ∆ ppm, calculate PREG and QREG using the following equation:
32768⋅8
1+ ∆ ⋅10−6
4⋅ PREG + QREG = floor
+ 0.5
For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG = 0x10040, and
QREG = 0x03. The default values of PREG and QREG, corresponding to zero adjustment, are 0x10000
and 0x0, respectively.
Default values for RTCA_ADJ, PREG and QREG should be nominal values, at the center of the ad-
justment range. Uncalibrated extreme values (zero, for example) can cause incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary.
The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one-second interrupt and
before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second
nominal clock periods, until the next one-second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurately set the RTC.
When setting the RTC_SEC register, it is important to take into account that the associated write operation
will be performed only in the next second boundary. This means that to set the RTC_SEC register to n,
the value n+1 has to be written. Similarly, increment and decrement operations need to be adjusted, i.e.
to increment the RTC_SEC register that is at count n, the value n+2 has to be written, and to decrement
the RTC_SEC register that is at count n, the value n has to be written.
1.4.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap re-
ference. If automatic temperature measurement is not performed by selecting CHOP_E = 00, the MPU
may request an alternate multiplexer frame containing the temperature sensor output by asserting
MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation re-
quired to offset the thermal drift in the system (see Section 3.5 Temperature Compensation).
1.4.5 Physical Memory
Flash Memory
The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6534H) of on-chip flash memory.
The flash memory primarily contains MPU and CE program code. It also contains images of the CE
RAM, MPU RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to
their respective locations.
The flash memory is segmented into individually erasable pages that contain 1024 bytes.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1 KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1 KB
boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].
Flash Write Procedures
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the
user in addition to external EEPROM.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
39
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
