FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Table 41: EECTRL Bits for 2-pin Interface
Read/ Reset
Write State
Status
Name
Bit
Polarity Description
7
6
5
4
ERROR
BUSY
R
R
R
R
0
0
1
1
Positive 1 when an illegal command is received.
Positive 1 when serial data bus is busy.
RX_ACK
TX_ACK
Negative 0 indicates that the EEPROM sent an ACK bit.
Negative 0 indicates when an ACK bit has been sent to the
EEPROM.
3:0
CMD[3:0]
W
0000 Positive
CMD[3:0]
Operation
0000
No-op command. Stops the I2C clock
(SCK, DIO4). If not issued, SCK
keeps toggling.
0010
Receive a byte from the EEPROM
and send ACK.
0011
0101
0110
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
1001
Issue a START sequence.
Others
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In
this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the
speed at which the SDA pin can be switched from output to input. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too
busy to process interrupts.
Three-wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX = 3. The EECTRL bits when the three-wire interface is selected are shown in
Table 42. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read
from the EEPROM, depending on the values of the EECTRL bits.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
Table 42: EECTRL Bits for the 3-wire Interface
Control
Bit
Read/
Write
Name
Description
7
WFR
W
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
6
5
4
BUSY
HiZ
R
W
W
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immedi-
ately after the last SCK rising edge.
RD
Indicates that EEDATA is to be filled with data from EEPROM.
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