71M6403
Electronic Trip Unit
SEPTEMBER 2006
Values read from and written into the DIO ports use the data registers P0, P1 and P2.
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 51 for DIO pins
available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for
pulse counting. The control resources selectable for the DIO pins are listed in Table 53. If more than one input is connected to
the same resource, the resources are combined using a logical OR.
DIO_R
Resource Selected for DIO Pin
Value
0
1
2
3
4
5
6
7
NONE
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
Table 53: Selectable Controls using the DIO_DIR Bits
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (STROBE = DIO6,
FAULT_PULSE = DIO7) using the I/O RAM registers DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and
DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I/O RAM
register DIO_EEX (0x2008[4]).
Physical Memory
Data bus address space is allocated to on-chip memory as shown in Table 54.
Address
(hex)
Wait States
(at 5MHz)
Memory Size
(bytes)
Memory
Memory Type
Typical Usage
Technology
Program and non-volatile
data
0000-FFFF
Flash Memory
Non-volatile
0
64KB
0000-07FF
1000-13FF
Static RAM
Static RAM
Battery-buffered
Volatile
MPU data XRAM,
CE data
0
5
2KB
1KB
configuration RAM
(I/O RAM)
2000-20FF
3000-3FFF
Static RAM
Static RAM
Volatile
Volatile
0
5
256
CE Program code
4KB
Table 54: MPU Data Memory Map
Flash Memory: The 71M6403 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
Page: 36 of 75
© 2006 TERIDIAN Semiconductor Corporation
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