71M6403
Electronic Trip Unit
SEPTEMBER 2006
VOLTAGE
BOOST
VDRV
GNDD
LCD_IBST
LCD_BSTEN
GNDD
V2P5NV
V3P3D
VOLT
REG
V3P3D
VBAT
GNDD
GNDD
V2P5
0.1V
V2P5
VLCD
Figure 7: LCD Voltage Boost Circuitry
UART (UART0) and Optical Port (UART1)
The 71M6403 includes an interface to implement an IR or optical port. The pin OPT_TX is designed to directly drive an external
LED for transmitting data on an optical link (low-active). The pin OPT_RX, also low-active, is designed to sense the input from an
external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port.
OPT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the OPT_TX output
is the I/O RAM register OPT_TXDIS (0x2008[5]).
Hardware Reset Mechanisms
Several conditions will cause a hardware reset of the 71M6403:
•
•
Voltage at the RESETZ pin low
Voltage at the E_RST pin low
Reset Pin (RESETZ)
When the RESETZ pin is pulled low, all digital activity in the chip stops while analog circuits are still active. Additionally, all I/O
RAM bits are cleared.
Hardware Watchdog Timer
In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware
watchdog timer (WDT) is included in the 71M6403. This timer will reset the MPU if it is not refreshed periodically, and can be
used to recover the MPU in situations where program control is lost.
The watchdog timer uses the RTC clock source as its time base and requires a reset under MPU program control at least every
1.3 (for CK38 = 38.4 kHz) seconds. When the WDT overflow occurs, the MPU is momentarily reset as if RESETZ were pulled
low for half of a clock cycle. Thus, after 4100 cycles of CK38, the MPU program will be launched from address 00.
An I/O RAM register status bit, WD_OVF (0x2002[2]), is set when WDT overflow occurs. This bit is powered by the VBAT
pin and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power up. After
reading this bit, MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin.
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© 2006 TERIDIAN Semiconductor Corporation
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