71M6403
Electronic Trip Unit
SEPTEMBER 2006
External Interrupts
The external interrupts are connected as shown in Table 43. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through
6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge
polarity shown in Table 43.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has
its own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44). The ZP8 interrupt must be cleared
by the MPU software. The ZP8 interrupt occurs every 853.4 msec.
External
Connection
Polarity
Flag Reset
Interrupt
0
1
2
3
4
5
6
Digital I/O High Priority
Digital I/O Low Priority
Comparator 2 or 3
Reserved
Comparator 2 or 3
EEPROM busy
ZP8
see DIO_Rx
see DIO_Rx
falling
automatic
automatic
automatic
rising
falling
falling
automatic
automatic
manual
Table 43: External MPU Interrupts
Interrupt 6 is edge-sensitive. The flag for the ZP8 interrupt is located in the WDI SFR (address 0xE8).
Enable Bit
EX0
Description
Flag Bit
IE0
IE1
IEX2
IEX3
IEX4
IEX5
IEX6
IE_ZP8
Description
Enable external interrupt 0
Enable external interrupt 1
Enable external interrupt 2
Enable external interrupt 3
Enable external interrupt 4
Enable external interrupt 5
Enable external interrupt 6
Enable ZP8 interrupt
External interrupt 0 flag
External interrupt 1 flag
External interrupt 2 flag
External interrupt 3 flag
External interrupt 4 flag
External interrupt 5 flag
External interrupt 6 flag
ZP8 interrupt flag
EX1
EX2
EX3
EX4
EX5
EX6
EX_ZP8
Table 44: Control Bits for External Interrupts
Page: 32 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
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