71M6403
Electronic Trip Unit
SEPTEMBER 2006
Because the watchdog timer uses CK38 as its clock reference, if the CK clock signal stops or slows down, WD_OVF is set and a
system reset will be performed when the CK clock resumes.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when
WAKE=0 and, during development, when a 0x14 command is received from the ICE port.
There is no internal digital state that deactivates the WDT. For debug purposes, the WDT can be disabled by tying the V1 pin to
V3P3. This also deactivates the power fault detection implemented with V1. Since there is no way in firmware to disable the
WDT, it is guaranteed that whatever state the MPU might find itself in, it will be reset to a known state upon watchdog timer
overflow.
V1
V3P3
WDT dis-
abled
V3P3-10mV
V3P3 -
400mV
Normal
operation,
WDT
enabled
when
(V1 < VBIAS)
the battery is
enabled
VBIAS = 1.6V
Battery or
reset
mode
0V
Figure 8: V1 Input Voltage Thresholds
Internal Voltages (VBIAS and V2P5)
The 71M6403 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages can
be tied together outside the chip. The internal supply voltage V2P5 is generated by an internal regulator from the 3.3V supplies.
VBIAS (1.6V) is generated internally and is used by the comparators V2 and INEUTRAL.
Page: 40 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
