TSC87251G1A
Table 23. Summary of Logical Instructions (1/2)
(1)
Logical AND
Logical OR
ANL <dest>, <src>
ORL <dest>, <src>
XRL <dest>, <src>
CLR A
dest opnd ← dest opnd Λ src opnd
dest opnd ← dest opnd V src opnd
dest opnd ← dest opnd src opnd
(A) ← 0
(1)
(1)
Logical Exclusive OR
(1)
Clear
(1)
Complement
CPL A
(A) ← (A)
Rotate Left
RL A
(A)
(A) ← (A)
← (A) , n= 0..6
n+1 n
0
7
Rotate Left Carry
RLC A
(A)
(CY) ← (A)
← (A) , n= 0..6
n+1 n
7
(A) ← (CY)
0
Rotate Right
RR A
(A) ← (A) , n= 7..1
n–1 n
(A) ← (A)
7
0
Rotate Right Carry
RRC A
(A) ← (A) , n= 7..1
n–1
n
(CY) ← (A)
0
(A) ← (CY)
7
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes
States
Bytes
States
A, Rn
register to ACC
1
2
1
2
2
3
3
3
4
5
4
4
5
5
4
4
1
1
1
1
1
1
1
2
2
2
2
2
3
2
2
3
4
3
3
4
4
3
3
1
1
1
1
1
1
2
(3)
(3)
A, dir8
A, @Ri
A, #data
dir8, A
dir8, #data
Rmd, Rms
WRjd, WRjs
Rm, #data
WRj, #data16
Rm, dir8
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A
Direct address (on–chip RAM or SFR) to ACC
Indirect address to ACC
1
1
2
1
3
1
Immediate data to ACC
(4)
(4)
ACC to direct address
2
2
(4)
(4)
Immediate 8–bit data to direct address
Byte register to byte register
Word register to word register
Immediate 8-bit data to byte register
Immediate 16-bit data to word register
Direct address to byte register
Direct address to word register
Direct address (64K) to byte register
Direct address (64K) to word register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Clear ACC
3
3
2
3
3
4
1
2
2
3
ANL
ORL
XRL
(3)
(3)
3
2
4
3
(5)
(5)
3
2
(6)
(6)
4
3
(5)
(5)
3
2
(5)
(5)
4
3
CLR
CPL
RL
1
1
1
1
1
1
1
1
1
1
1
1
A
Complement ACC
A
Rotate ACC left
RLC
RR
A
Rotate ACC left through CY
Rotate ACC right
A
RRC
A
Rotate ACC right through CY
Notes:
1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
19
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
