TSC87251G1A
Table 21. Summary of Increment and Decrement Instructions
Increment
Increment
Decrement
Decrement
INC <dest>
INC <dest>, <src>
DEC <dest>
dest opnd ← dest opnd + 1
dest opnd ← dest opnd + src opnd
dest opnd ← dest opnd – 1
DEC <dest>, <src>
dest opnd ← dest opnd – src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
A
ACC by 1
1
1
2
1
3
3
3
3
1
1
1
1
2
2
2
2
2
2
2
1
1
2
Rn
Register by 1
INC
DEC
(2)
(2)
dir8
Direct address (on–chip RAM or SFR) by 1
Indirect address by 1
2
2
@Ri
3
2
2
4
5
1
4
1
1
3
4
1
Rm, #short
WRj, #short
DRk, #short
DRk, #short
DPTR
Byte register by 1, 2, or 4
INC
DEC
Word register by 1, 2, or 4
Double word register by 1, 2, or 4
Double word register by 1, 2, or 4
Data pointer by 1
INC
DEC
INC
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Compare
CMP <dest>, <src>
dest opnd – src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
Rmd, Rms
Register with register
3
3
3
4
5
5
2
3
5
3
4
6
2
2
2
3
4
4
1
2
4
2
3
5
WRjd, WRjs
DRkd, DRks
Rm, #data
Word register with word register
Dword register with dword register
Register with immediate data
WRj, #data16
DRk, #0data16
Word register with immediate 16-bit data
Dword register with zero-extended 16-bit immediate
data
CMP
DRk, #1data16
Rm, dir8
Dword register with one-extended 16-bit immediate data
Direct address (on–chip RAM or SFR) with byte register
5
4
4
6
4
3
3
5
(1)
(1)
3
2
WRj, dir8
Direct address (on–chip RAM or SFR) with word
register
4
3
(2)
(2)
Rm, dir16
Direct address (64K) with byte register
Direct address (64K) with word register
Indirect address (64K) with byte register
Indirect address (16M) with byte register
5
5
4
4
3
4
4
3
3
2
(3)
(3)
WRj, dir16
Rm, @WRj
Rm, @DRk
4
3
(2)
(2)
3
2
(2)
(2)
4
3
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
18
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
