APPENDIX A
FORMS A PART OF SMD 5962-89598
FUNCTIONAL ALGORITHMS
10. SCOPE
10.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns
be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms
shall be applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The
information contained herein is intended for compliance.
20. APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
30. ALGORITHMS
30.1 Algorithm A (pattern 1).
30.1.1 Checkerboard, checkerboard-bar.
Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum.
Step 2. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum.
Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum.
Step 4. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to
maximum.
30.2 Algorithm B (pattern 2).
30.2.1 March.
Step 1. Load memory with background data, incrementing from minimum to maximum address locations (All
"0's").
Step 2. Read data in location 0.
Step 3. Write complement data to location 0.
Step 4. Read complement data in location 0.
Step 5. Repeat steps 2 through 4 incrementing X-fast sequentially, for each location in the array.
Step 6. Read complement data in maximum address location.
Step 7. Write data to maximum address location.
Step 8. Read data in maximum address location.
Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for, each location in the array.
Step 10. Read data in location 0.
Step 11. Write complement data to location 0.
Step 12. Read complement data in location 0.
Step 13. Repeat steps 10 through 12 decrementing X-fast sequentially for each location in the array.
Step 14. Read complement data in maximum address location.
Step 15. Write data to maximum address location.
Step 16. Read data in maximum address location.
Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array.
Step 18. Read background data from memory, decrementing X-fast from maximum to minimum address locations.
SIZE
STANDARD
5962-89598
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
L
SHEET
43
DSCC FORM 2234
APR 97
TEMIC [ TEMIC SEMICONDUCTORS ]
