12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
2
3
4
5
6
7
8
TC7109
TC7109A
2
3
40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
25
24
23
22
21
+
XTALI
XTAL2
–
–
+
–
+5V
V
REF IN
REF CAP
REF CAP
1
4
5
6
2
+5V
TO
GND
GND
EXTERNAL
REFERNCE
1µF
1MΩ
17
RESET
SS
TEST
21–24,
35–38
+
+
P20–P27
REF IN
8
5
+
IN HI
INT
8748/8049
CMOS
MICROCOMPUTER
INPUT
–
0.01µF
OTHER I/O
HI LO
COM
ANALOG
GND
TC7109A
C
7
8
31–34
INT
GND
P14–P17
EA
INT
0.15µF
C
AZ
0.33µF
AZ
WR
9
30
29
28
27
26
2
BUFF
REF OUT
PSEN
ALE
P13
P12
P11
P10
RUN/HOLD
STATUS
LBEN
R
11
25
26
39
40
INT
18
19
20kΩ 0.2 V
REF
–
+5V
+5V
+5V
+5V
–5V
V
PROG
10 kΩ 1 V
REF
SEND
V
HBEN
DD
BUFF OSC OUT
TL
3–8
B9–B12,
POL, OR
GND
V
OSC SEL
OSC OUT
OSC IN
CC
6
8
3.58MHz
CRYSTAL
12–19
10
9–16
20
B1–B8
DB0–DB7
RD
8
20
GND
CE/LOAD
GND
MODE
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
Signal-Integrate Phase
DETAILED DESCRIPTION
The buffer and integrator inputs are removed from
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage be-
tween input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct common-
mode voltage.
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V+. Each measurement cycle is
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero(AZ), (2)SignalIntegrate(INT), (3)Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Deintegrate Phase
Input high is connected across the previously-charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the ca-
pacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (estab-
lished by auto-zero) with a fixed slope. The time, repre-
sentedbythenumberofclockperiodscountedfortheoutput
to return to zero, is proportional to the input signal.
Auto-Zero Phase
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the refer-
ence voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, CAZ, to compensate for
offset voltage in the buffer amplifier, integrator, and com-
parator. Since the comparator is included in the loop, the AZ
accuracyislimitedonlybythenoiseofthesystem.Theoffset
referred to the input is less than 10 µV.
TELCOM SEMICONDUCTOR, INC.
3-97
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
