12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC7109
TC7109A
AUTO-ZERO
PHASE I
DETERMINATED
AT ZERO CROSSING
DETECTION
STATIC IN
MIN 1790 COUNTS
HOLD STATE
MAX 2041 COUNTS
INT
PHASE II
INTEGRATOR OUTPUT
7 COUNTS
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
RUN/HOLD INPUT
*
*NOTE: RUN/HOLD input is ignored until end of auto-zero phase.
Figure 5. TC7109A RUN/HOLD Operation
The RUN/HOLD input may be used to shorten conver-
sion time. If RUN/HOLD goes LOW any time after zero
crossing in the deintegrate mode, the circuit will jump to
auto-zero and eliminate that portion of time normally spent
in deintegrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in deintegrate. It will stay in
auto-zero for the minimum time and wait in auto-zero for a
HIGH at the RUN/HOLD input. As shown in Figure 5, the
STATUS output will go HIGH 7 clock periods after RUN/
HOLD is changed to HIGH, and the converter will begin the
integrate phase of the next conversion.
data accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 6 and Table 1.)
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
t
CEA
CE/LOAD
AS INPUT
t
BEA
HBEN
AS INPUT
The RUN/HOLD input allows controlled conversion in-
terface. The converter may be held at idle in auto-zero with
RUN/HOLD LOW. The conversion is started when RUN/
HOLD goes HIGH, and the new data is valid when the
STATUS output goes LOW (or is transferred to the UART;
see "Handshake Mode"). RUN/HOLD may now go LOW,
terminating deintegrate and ensuring a minimum auto-zero
timebeforestoppingtowaitforthenextconversion. Conver-
sion time can be minimized by ensuring RUN/HOLD goes
LOW during deintegrate, after zero crossing, and goes
HIGHaftertheholdpointisreached. Therequiredactivityon
the RUN/HOLD input can be provided by connecting it to the
buffered oscillator output. In this mode, the input value
measured determines the conversion time.
LBEN
AS INPUT
t
t
DAB
DAB
DATA
VALID
DATA
VALID
HIGH-BYTE
DATA
t
t
DHC
DAC
LOW-BYTE
DATA
DATA
VALID
= HIGH IMPEDANCE
Figure 6. TC7109A Direct Mode Output Timing
Table 1. TC7109A Direct Mode Timing Requirements
Symbol Description Min Typ Max Units
tBEA
tDAB
Byte Enable Width
200 500
150
nsec
nsec
Direct Mode
Data Access Time
From Byte Enable
300
300
The data outputs (bits 1 through 8, low-order bytes; bits
9 through 12, polarity and overrange high-order bytes) are
accessible under control of the byte and chip enable termi-
nals as inputs with the MODE pin at a LOW level. These
three inputs are all active LOW. Internal pull-up resistors are
provided for an inactive HIGH level when left open. When
chip enable is LOW, a byte-enable input LOW will allow the
outputs of the byte to become active. A variety of parallel
tDHB
Data Hold Time
From Byte Enable
150
nsec
tCEA
tDAC
Chip Enable Width
300 500
200
nsec
nsec
Data Access Time
From Chip Enable
400
400
tDHC
Data Hold Time
From Chip Enable
200
nsec
3-100
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