12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
2
3
4
5
6
7
8
TC7109
TC7109A
ZERO CROSSING OCCURS
ZERO CROSSING DETECTED
POSITIVE TRANSITION
CAUSES ENTRY INTO
UART MODE
STATUS OUTPUT UNCHANGED
IN UART MODE
LATCH PULSE INHIBITED
IN UART MODE
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
DE PHASE III
MODE INPUT
UART
TERMINATES
UART MODE
NORM
SEND
SENSED
SEND
SENSED
SEND
SENSED
INTERNAL MODE
SEND INPUT
CE/LOAD AS OUTPUT
HBEN
HIGH-BYTE DATA
LBEN
DATA VALID
LOW-BYTE DATA
DATA VALID
THREE-STATE
HIGH IMPEDANCE
THREE-STATE
WITH PULL-UP
=
=
= DON'T CARE
Figure 9. TC7109A Handshake Triggered by MODE Input
Oscillator
Theoscillatormaybeoverdriven,ormaybeoperatedas
an RC or crystal oscillator. The OSCILLATOR SELECT
input optimizes the internal configuration of the oscillator for
RC or crystal operation. The OSCILLATOR SELECT input
is provided with a pull-up resistor. When the OSCILLATOR
SELECT input is HIGH or left open, the oscillator is config-
ured for RC operation. The internal clock will be the same
frequency and phase as the signal at the BUFFERED
OSCILLATOR OUTPUT. Connect the resistor and capaci-
tor as in Figure 10. The circuit will oscillate at a frequency
given by f = 0.45/RC. A 100 kΩ resistor is recommended for
useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an integral
multiple of the 60 Hz period for optimum 60 Hz line rejection.
With OSCILLATOR SELECT input LOW, two on-chip
capacitorsandafeedbackdeviceareaddedtotheoscillator.
In this configuration, the oscillator will operate with most
crystalsinthe1to5MHzrangewithnoexternalcomponents
(Figure 11). The OSCILLATOR SELECT input LOW inserts
a fixed Ϭ58 divider circuit between the BUFFERED OSCIL-
LATOR OUTPUT and the internal clock. A 3.58 MHz TV
crystal gives a division ratio providing an integration time
given by:
58
3.58 MHz
t = (2048 clock periods)
= 33.18 ms
The error is less than 1% from two 60 Hz periods, or
33.33 ms, which will give better than 40 dB, 60 Hz rejection.
The converter will operate reliably at conversion rates up
to 30 per second, corresponding to a clock frequency of
245.8 kHz.
When the oscillator is to be overdriven, the OSCILLA-
TOR OUTPUT should be left open, and the overdriving
signal should be applied at the OSCILLATOR INPUT. The
internal clock will be of the same duty cycle, frequency and
phaseastheinputsignal.WhentheOSCILLATORSELECT
is at GND, the clock will be 1/58 of the input frequency.
TELCOM SEMICONDUCTOR, INC.
3-103
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
