DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B –JULY 2012–REVISED APRIL 2013
1.8V
1.8V
10k
10k
R
ID1
R
ID0
V
DDIO
IDx[0]
IDx[1]
RPU
RPU
HOST
DS90UB914Q
SCL
SDA
SCL
SDA
To other
Devices
Figure 35. ID[x[ Address Decoder on the Deserializer
Table 8. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q Deserializer
ID[x] Resistor Value — DS90UB913Q Serializer
Resistor RID1 Ω
(1%Tolerance)
Resistor RID0 Ω
(1%Tolerance)
Address 7'b
Address 8'b 0 appended
(WRITE)
0k
0k
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0xC0
0xC2
0xC4
0xC6
0xC8
0xCA
0XCC
0XCE
0XD0
0XD2
0XD4
0XD6
0XD8
0XDA
0XDC
0XDE
0k
3k
0k
11k
100k
0k
0k
3k
3k
3k
3k
11k
100k
0k
3k
11k
11k
11k
11k
100k
100k
100k
100k
3k
11k
100k
0k
3k
11k
100k
Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input and LOCK is TRI-
STATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q completes its lock
sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered
from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on
the OEN and OSS_SEL setting (Table 5). See Figure 19.
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