DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
Deserializer – Adaptive Input Equalization(AEQ)
The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media.
The level of equalization can also be manually selected via register controls. The fully adaptive equalizer output
can be seen using the CMLOUTP/CMLOUTN pins in the Deserializer.
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SERIAL LINE FREQUENCY (MHz)
Figure 39. Maximum Equalizer Gain vs. Line Frequency
EMI Reduction
Deserializer Staggered Output
The receiver staggers output switching to provide a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and
helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
Spread Spectrum Clock Generation(SSCG) on the Deserializer
The DS90UB914Q parallel data and clock outputs have programmable SSCG ranges from 10 MHz to 100 MHz.
The modulation rate and modulation frequency variation of output spread is controlled through the SSC control
registers on the DS90UB914Q device. SSC profiles can be generated using bits [3:0] in register 0x02 in the
Deserializer.
Powerdown
The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by
the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if
the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the
SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed
driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device.
This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also
available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops.
When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output
valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration.
Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
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