DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
www.ti.com
Bus Activity:
Master
Register
Address
Slave
Address
Data
SDA Line
7-bit Address
P
S
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Figure 29. Write Byte
N
A
C
K
Bus Activity:
Master
Register
Address
Slave
Address
Slave
Address
S
P
SDA Line
S
7-bit Address
7-bit Address
0
1
A
C
K
A
C
K
A
C
K
Data
Bus Activity:
Slave
Figure 30. Read Byte
ACK
LSB
MSB
N/ACK
SDA
SCL
MSB
LSB
R/W
Direction
7-bit Slave Address
Data Byte
Bit
Acknowledge
*Acknowledge
or Not-ACK
from the Device
8
9
8
9
1
2
6
7
1
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START
STOP
Figure 31. Basic Operation
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 32. Start and Stop Conditions
Slave Clock Stretching
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control To communicate and synchronize with remote
devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913/914Q chipset.
42
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
