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DS90UB913QSQ/NOPB 参数 Datasheet PDF下载

DS90UB913QSQ/NOPB图片预览
型号: DS90UB913QSQ/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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DS90UB913Q, DS90UB914Q  
www.ti.com  
SNLS420B JULY 2012REVISED APRIL 2013  
Camera A  
Slave ID: (0xA0)  
DS90UB913Q  
DS90UB914Q  
ROUT[11:0],  
HS, VS,  
PCLK  
CMOS  
Image  
Sensor  
DIN[11:0]  
, HS, VS,  
PCLK  
2
2
SDA  
SCL  
SDA  
SCL  
I C  
I C  
DES A: ID[x](0xC0)  
SLAVE_ID1_MATCH(0xA0)  
SLAVE_ID1_INDEX(0xA0)  
SLAVE_ID2_MATCH(0xA2)  
SLAVE_ID2_INDEX(0xA2)  
DS90UB914Q  
SER A: ID[x](0xB0)  
mC/  
EEPROM  
ECU  
Module  
Slave ID: (0xA2)  
Camera B  
Slave ID: (0xA0)  
DS90UB913Q  
DIN[11:0]  
, HS, VS,  
PCLK  
ROUT[11:0],  
HS, VS,  
PCLK  
CMOS  
Image  
Sensor  
2
2
SDA  
SCL  
SDA  
SCL  
I C  
I C  
mC  
mC/  
SER B: ID[x](0xB2)  
DES B: ID[x](0xC2)  
EEPROM  
SLAVE_ID2_MATCH(0xA4)  
SLAVE_ID2_INDEX(0xA0)  
SLAVE_ID2_MATCH(0xA6)  
SLAVE_ID2_INDEX(0xA2)  
Master  
Slave ID: (0xA2)  
Figure 36. Multiple Device Addressing  
Synchronizing Multiple Cameras  
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General  
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To  
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical  
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize  
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of  
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from  
the birectional control channel, there will be a time variation of the GPIO signals arriving at the different target  
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across  
multiple links is 25µs.  
Note: The user must verify that the timing variations between the different links are within their system and timing  
specifications.  
See Figure 37 for an example of this function.  
The maximum time (t1) between the rising edge of GPIO (i.e. sync signal) arriving at Camera A and Camera B is  
25µs.  
Copyright © 2012–2013, Texas Instruments Incorporated  
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47  
Product Folder Links: DS90UB913Q DS90UB914Q  
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