DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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DS90UB913Q
Camera A
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
Serializer A
Deserializer A
ECU
Module
Camera B
DS90UB913Q
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
mC
Serializer B
Deserializer B
Figure 37. Synchronizing Multiple Cameras
DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t1
Figure 38. GPIO Delta Latency
General Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the Serializer and 4 GPIOs on the Deserializer when the DS90UB913/914Q chipsets are
run off the pixel clock from the imager as the reference clock source. The GPOs on the Serializer can be
configured as outputs for the input signals that are fed into the Deserializer GPIOs. In addition, the GPOs on the
Serializer can behave as outputs of the local register on the Serializer. The GPIOs on the Deserializer can be
configured to be the input signals feeding the output of the GPOs on the Serializer. In addition the GPIOs on the
Deserializer can be configured to behave as outputs of the local register on the Deserializer. If the
DS90UB913/914Q chipsets are run off the external oscillator source as the reference clock, then GPO3 on the
Serializer is automatically configured to be the input for the external clock and GPIO2 on the Deserializer is
configured to be the output of the divide-by-2 clock which is fed into the imager as its reference clock. In this
case, the GPIO2 and GPIO3 on the Deserializer can only behave as outputs of the local register on the
Deserializer. The GPIO maximum switching rate is up to 66 kHz when configured for communication between
Deserializer GPIO to Serializer GPO.
LVCMOS VDDIO Option
1.8V/2.8V/3.3V Serializer inputs and 1.8V/3.3V Deserializer outputs are user configurable to provide compatibility
with 1.8V, 2.8V and 3.3V system interfaces.
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